FPGA dev claims the Neo Geo AES+ is "basically the MiSTer core" broken up into separate chips

It's no surprise that the Neo Geo AES+ is raising a few eyebrows, especially given its promise to recreate the retro console without using emulation or FPGA. However, it turns out the arcade system's ASIC chips are based on existing FPGA code, and one developer says Plaion is pulling a "bait and switch."

For context, the Neo Geo AES+ is set to replicate the board of the '90s console using ASICs (Application-Specific Integrated Circuit) programmed for one specific task. In this instance, the chips will be serving in place of SNK's original graphics chips that handle sprites, color pallets, and communication with other components like the CPU, but FPGA developer Pramod Somashekar believes Plaion is "basically the mister core" that's divided up into separate ICs.

The claim itself is in response to a post revealing that the Neo Geo AES ASICs are using code by FPGA developers Furrtek and Jotego (cheers, Time Extension). In response, Somashekar says, "That means this is basically the mister core, but instead of having the design on one FPGA you break it up into multiple ASICs," before accusing the retro console makers of the aforementioned "bait and switch" that contradicts the system's marketing.

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Yes, the debate over whether the Neo Geo AES+ is using tech close to the original hardware, or simply repackaging existing FPGA cores, is getting spicy. While Somashekar seems to subscribe to the latter, Furrtek, who is a renowned expert within the realm of Neo Geo reverse engineering, suggested Plaion's remake "has every chance of being the best since SNK themselves stopped manufacturing hardware," in a now-deleted Tweet.

That take was included in the original Time Extension report, with the FPGA developer adding, "Perfect, maybe not, but certainly with the ambition to do better than emulation, to honour the brand, and to respect the fans." In response to that article, Furrtek has also clarified that they meant it "offers more than what's already available" and says "a simple repackaging of MAME or the MiSTer core would be a bit sad."

Furrtek's reply helps quash the idea that the Neo Geo AES+ is just the existing MiSTer core split into separate chips. For more casual players, the argument will really sound like splitting hairs, especially since custom ASICs and FPGA share the same goal of authentically replicating the original retro console hardware with 100% accuracy. However, Somashekar makes the point that since the chips are "hard-wired", they can't be dynamically configured like Field Programmable Gate Arrays, meaning they can't be updated.

NEOGEO AES+ Announce Trailer [ENG-PEGI] - YouTube

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I'll admit that the latter idea of bugs or issues being forever baked into the Neo Geo AES+ gives me the heebies. It's really the main reason you should even care about the remake not using the exact original hardware or an FPGA that can be patched, as it leaves room for mistakes that then can't be corrected. That fear is based on the assumption that Plaion won't end up engineering ASICs that act exactly like the original custom chips, and with experts like Jotego and Furrtek on board, I'm feeling optimistic.

On a related note, Commodore has signalled that it will block custom C64 Ultimate FPGA firmware in the future, which could hinder your DIY microcomputing plans.

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